Integrated circuit designs typically undergo a variety of design verification steps before the manufacturing process begins to ensure that the design meets all design goals. This evaluation process allows designers to identify design shortcomings without the cost and delay of actually building integrated circuit devices prior to performing any evaluation. This is particularly important for complex integrated circuits, such as microprocessors, because such circuits are extremely costly and time-consuming to design and fabricate.
A known method of performing full-chip verification on a logic design is to employ a timing verifier to evaluate a software model of the design and verify that the operation of the design falls within predetermined parameters based on the operation of the software model. The results of this evaluation are then compared to the desired timing specifications for the new designs so that modifications to the design, if necessary, can be made before fabrication of the chip. To perform full-chip verification in this manner, the verification procedure must evaluate the design of the circuitry connecting different functional areas (sections) of the integrated circuit together.
As will be appreciated by one of ordinary skill in the field, the complexity and cost of performing full-chip timing verification increases as the complexity of the integrated circuit design being verified increases. The time required to perform and analyze the timing characteristics on new chip designs, such as designs for microprocessors, has increased substantially in recent years. Full-chip verification for microprocessors requires long run times and large amounts of system memory to stimulate operation of the integrated circuit design. Full-chip analysis also requires analysis of large numbers of critical paths between section boundaries. In some instances, full-chip verification takes so long that cost constraints dictate reducing the number of verified parameters for each design.
On the other hand, there are significant advantages to performing full-chip analysis instead of a reduced level of verification. One such advantage is that full-chip verification provides an acceptable level of verification for high performance designs that contain many critical paths that span section boundaries. Full-chip verification also allows savings in fabrication costs if a design is found to be infeasible early in the design cycle.
One known method of reducing the time and expense of full-chip verification is to perform verification on individual sections of a complex integrated circuit design. Verification of sections takes less time than full-chip verification because each functional area of the integrated circuit obviously has fewer logic circuits than the integrated circuit as a whole. A problem with the philosophy of section-level verification is that timing failures caused by the interaction of different sections of the integrated circuit is often overlooked or inadequately evaluated, resulting in higher costs later in the design cycle. The relationships among inter-section timing parameters are known in the field as "bristle timing."
As an alternative to pure section-level verification, manual methods of integrating section-level verification with some degree of full-chip verification are known in the field. One such method is to manually maintain section-level bristle timing in verification procedures to partially and crudely analyze the interaction between different sections of the integrated circuit. This methodology has an advantage over section-level verification because it provides some degree of evaluation of the interaction between different sections of the circuit design. Nonetheless, manual maintenance of bristle timing parameters is more inefficient than section-level verification because bristle timing parameters cannot be manually maintained with precision. Multiple verification procedures with cycle time variation are not practical if bristle timing is maintained manually.
Additionally, changes in the design of one section of a microprocessor potentially result in a need to manually update bristle timing. This process is prone to error. Thus, known methods of integrating section-level and full-chip verification fall to provide the complete benefits of either section-level or full-chip verification. A method of integrating the desirable aspects of section-level verification and full-chip verification for VLSI integrated circuit devices that avoids the aforementioned problems is desirable.